Sorry for the late response.
@robertferanec @Paul van Avesaath Thanks for your inputs, and that's a great application note there.
Sticking with JLC2313 but the setup now is S-G-S-G-S-G, and I can use 4/4.5 mil for 50 ohms.
Both the data banks are routed on L3. Bank 0 track length varies from 570 mills to 710 mils and 510 to 650 mils on bank1 Will length match them.
Couldn't route all the signals in ACC to the first chip without using vias, Used layer 3 and 5 for to route ACC group.
ACC on L5
Layer 3 ACC
Placed GND vias around signal transition, are they sufficient? DRAM clock over 533MHz is considered as OC (Allwinner's manual), not looking for anything above 667 :'D
Here's Termination and DRAM CLK, Clock is routed on top layer and switches to L5 at 1st DRAM. I will calculate the required delay and match it to ACC. Before I run xSignals and length match the signals groups I had few things to clarify.
1) I have a tight spot where an ODT signal crosses DRAM_CLK right through the via, but are routed on different layers. How bad is this?
2) Using about 0.7mm dia anti pad and I was going through openRex layout anti pad is as big as the via pad. Should I follow the same, will have better reference around vias
3) Should I put the data banks on a different layer? As there is no split power plane to deliver power, was saving that area to route power through thick tracks.
I highly appreciate any inputs and suggestions! Also included PCBdoc!