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ddr3 flyby matching CKE and RESET address and control

diegopm , 06-15-2017, 04:44 PM
I have a question about length matching of the CKE and RESET signals in a DDR3 BUS using a flyby topology.
Is it necessary to match length these signals?
I realize that Altium designer do not include this signals when using the xsignal wizard, on the other hand, I have taken a look some designs and some of them has RESET and CKE matched with all others address and control signals. So I don’t know if I am configuring something wrong in xsignal wiward.

robertferanec , 06-16-2017, 12:47 AM
We do not length match RESET, but we do keep it similar length as ADDR/CMD/CTL (it is usually routed together with these signals, so the length is similar). However, we use a bigger gap/clearance between RESET and other neighbor signals.
diegopm , 06-16-2017, 01:26 AM
Thanks Robert,
What are about CKE?
robertferanec , 06-18-2017, 12:48 AM
CKE must be length matched - it is in the Control signal (CTL) group. Here is an example of DDR3 groups (pages 41 and 42): http://cache.nxp.com/assets/document...6DQ6SDLHDG.pdf
Via, 12-15-2017, 12:40 PM
When Altium xSignal choice the address and data signals there is not CKE on it! I draw my DDR3 fly-by tracks with xSignal but leaved CKE! without length maching with other control signal! I sent my board to manufacturer, it maybe doesn't work?
diegopm , 06-18-2017, 03:35 AM
Ok, I have discover that it is possible to add manually new xsingnals. Altium xsignals wizard do not include CKE by default.
Via, 12-15-2017, 12:41 PM
Why xSignal feature did not add CKE as DDR3 control signal!! ?
robertferanec , 12-15-2017, 12:42 PM
Why xSignal feature did not add CKE as DDR3 control signal!! ?
@Via, maybe a bug?
Via , 12-15-2017, 01:33 PM
I checked my reference design made by KiCAD software,The DDR3 chip that I used is just use CKE0
I think maybe for DDR3 Chip that don't have CKE1 ( more than 1G memory size) maybe is not need to length matching CKE signal!
Via , 12-15-2017, 01:35 PM
Originally posted by robertferanec
@Via, maybe a bug?
I did not think so, xSignal detect all signal between two chips, I used a lot!
Via , 12-15-2017, 02:09 PM
Here is Length matching for Olimex-A64 !
What do you think?
robertferanec , 12-18-2017, 06:19 PM
I have not used A64. I am not sure what are the recommendations for length matching. Each chip is different and it is important to check documentation.
Via , 12-20-2017, 10:27 AM
Thank you Robert for all your help and consideration!
Via , 12-26-2017, 09:37 PM
Finally, the processor detected 1G memory and boot to Linux!
That was so great! Without CKE length matching!
Robert Thankkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk youuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu uuuuuuuuuuuuuuu!
robertferanec , 12-27-2017, 11:48 AM
Did you put the CKE to pernament Low? Or what helped?
Via , 12-27-2017, 04:36 PM
I did not change anything on board!
Is actually always Hi, I have another issue that shutdown command just reset the board!
I'm not think so that has relation to CKE signal!
Mihai , 08-06-2019, 06:23 AM
Hi @robertferanec ,

So, as I see here and also find in your public design the DDR reset signal is not length matched to the CTRL and ADDR group (also there are no rules in the design guides about it, at least I didnt see them). However, I see that you have routed it on a different layer with respect to the CTRL and ADDR group(e.g. OpenRex project). How critical is this signal in terms of length or timing? I am planning to routed it with high clearance and almost the same length but on a different layer (bottom instead of an inner layer), due to the lack of space.

robertferanec , 08-06-2019, 09:04 AM
I believe, RESET is asynchronous and it doesn't need to be length matched. I believe, routing RESET on different layers should be fine - just be aware of neighbor signals and possible crosstalk.
Mihai , 08-06-2019, 09:06 AM
Indeed, that's what I was thinking, but I was looking to have also an answer from you, just to be sure.
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