Platform forum

length tunning

mostafa222 , 04-18-2017, 10:10 PM
Hi dear robert. I tuned my ddr3 data track within each bank but each bank have diffrent track size. Is it necessary to make all bank size the same? Or only track within each bank must be tuned?
mairomaster , 04-19-2017, 01:43 AM
Only the tracks within a bank need to be matched, banks can have different overall length. Make sure you length match DQS and DM signals as well, together with the DQ signals in a bank. Also make sure you match the two signals in the DQS differential pair tightly.
robertferanec , 04-19-2017, 11:55 AM
Follow the @mairomaster's advice. Also, you may need to meet two more rules:
- a rule which specify the shortest possible track length for data signal (this may be specified for some designs)
- a rule which specify the longest possible track length for data signal (it's usually related to clock length)

So be careful, that the track in your banks also meet these two additional rules.

This picture may help: http://www.fedevel.com/welldoneblog/...atching-rules/
mostafa222 , 04-19-2017, 11:22 PM
Thank you so much
MadhuWesly , 06-23-2017, 10:17 PM
Hi Robert, Can you please clarify the following: 1. Should we draw all the Address/Command signals on same layer(single layer)? Should n't I draw on different layers for making my layout easy? 2. Do we need to length match Address/ Command signals, Will the primary length match be sufficient? 3. What will be the problem if I draw DQS and DM signals in a bank on different layers(but with matched length) instead of drawing along with the byte lane? Awaiting your reply...
robertferanec , 06-26-2017, 12:19 AM
Hi @MadhuWesly, what interface we are speaking about? DDR3?

​1) Route them the same way. It doesn't mean they are routed on 1 layer, may would not be possible. It means, all signal within group should go through same layers.
2) If we are speaking about DDR3 interface, yes they should be length match. Have a look for example at this document: http://cache.nxp.com/docs/en/user-gu...6DQ6SDLHDG.pdf
3) I would not recommend that. Your memory interface may not work reliably.

The best may be, if you have a look at layout of our iMX6 Rex board. You can download the Altium files and check the memory signals: http://www.imx6rex.com/
MadhuWesly , 06-26-2017, 03:12 AM
Thank you so much, Robert.
I was speaking about DDR3(actually DDR3L) only. Yes, in the HD guide it is given that Address and command signal as one group and Control signals as one group.
So, can I draw all the address and command signals on one layer and all the control signals(CS, CKE, ODT) along with RESET(not mentioned in any group) signal( except clock) on another layer?
robertferanec , 06-26-2017, 10:30 AM
You can route ADDR /CMD (DRAM_A[15:0] DRAM_SDBA[2:0] DRAM_RAS DRAM_CAS DRAM_SDWE) and CTRL (DRAM_CS[1:0] DRAM_SDCKE[1:0] DRAM_SDODT[1:0]) different way. Normally we route these groups same way and use the rule which is more strict. We do not length match RESET, but we often route it same way as ADDR/CMD/CTL.

PS: I am not really sure what you mean by "one layer" or "another layer" ... the signals can be routed on multiple layers
MadhuWesly , 06-26-2017, 10:55 AM
Thank you, Robert.

In the previous post, what I meant was, "Can I draw the two groups(ADDR/CMD and CTRL) of signals on different layers(for eg: consider 8 layer, ADDR/CMD on one of the signal layers and CTRL signal group on some other signal layer), but they are drawn in the same way by maintaining matched length"?
robertferanec , 06-26-2017, 11:35 PM
Oki, I understand
Use our interactive Discord forum to reply or ask new questions.
Discord invite
Discord forum link (after invitation)

Didn't find what you were looking for?