Hi @MadhuWesly, what interface we are speaking about? DDR3?
â€‹1) Route them the same way. It doesn't mean they are routed on 1 layer, may would not be possible. It means, all signal within group should go through same layers.
2) If we are speaking about DDR3 interface, yes they should be length match. Have a look for example at this document: http://cache.nxp.com/docs/en/user-gu...6DQ6SDLHDG.pdf
3) I would not recommend that. Your memory interface may not work reliably.
The best may be, if you have a look at layout of our iMX6 Rex board. You can download the Altium files and check the memory signals: http://www.imx6rex.com/