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VIA and uVIA

walid , 11-08-2016, 08:54 AM
Hello Reobert,

Would it be possible please to give a numerical example on how did you calculate the spacing between the two memories (Video L7/00:19:17)?

Another question I have is how to calculate the size of VIAs to handle a specific flow current?

Does the size of VIA and VIA type has to do with crosstalk and signal integrity?

Why do you always need to set the Vias with Soldermask Mask Expansion value? Does this means the VIA cuper will be exposed or tainted with soldermask? I always try to force complete tainting for VIAs, which gives the PCB better look.

The design rules for uVIA is not really clear. Would you please elaborate more on that? Or if your have a short video explain that please let me know and I will take a look.

Do you think it is a good practice to use micro-VIAs for Power Tracks?

Have you ever recorded a video that illustrates the whole components placement and routing process? You don't need to explain anything. Just record your screen and whoever is watching the video will learn a lot out of the process without any explanation. In the same time the learner may try to mimic the process. This would be the best practice ever.

Thank you a lot Robert.
robertferanec , 11-10-2016, 09:42 AM
1) Spacing between memories:
It depends on project and number of layers which you can use. If memories are using T-Branch topology, then the simple way to calculate approximate space between memories is (number of tracks in CMD+CTRL+ADDR+RESET + 1) * track width / gap * 2 + some space for decoupling capacitor VIAs. However, memories can be also placed closer, but it is more difficult to route and more layers may need to be used.

If they are using Fly-By, the chips can be placed almost near to each other (you may need to add some space for decoupling capacitors and some space to cover memory package size difference).

I recommend you to have a look at JEDEC examples (http://www.fedevel.com/welldoneblog/...yout-examples/) or our open source designs http://www.imx6rex.com/

2) There are couple of online tools, but simple and useful is to install Saturn PCB Toolkit. It's a free software and has a lot of useful calculators.

3) For high speed signals you would like to minimize number of VIAs in the tracks and also you may need to consider influence of stubs in the VIAs. I do not really work with "size" of VIA - for signals we always use the smallest easy to manufacture VIAs (e.g. 0.45mm pad / 0.2mm drill for through hole or 0.27mm / 0.1mm for uVIA ). I do consider using uVIAs / buried VIAs if it is possible to eliminate VIA stub when routing between particular layers.

4) You can do tainted VIAs, the result is same as changing Solder Mask Expansion value.

5) I am not sure what do you mean by design rules for uVIAs.

6) I never use uVIAs for power tracks

7) We have this: i.MX6 Module Layout – Complete PCB Routing [Video]
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