This is the manufacturer we normally use at our company:
Different things need to be considering when working with such small clearances:
- Copper to copper clearance - probably the most obvious one. The value might need to be more on plated layers (top and bottom for example, but could be some others as well), since because of the plating they cannot achieve such a good accuracy. The values for plated and non-plated layers are normally given by the PCB manufacturer. It also depends which technology you want to use, for better technologies you are getting better values, but you pay more. With Stevenage we can get down to 50 um for none-plated layers and 76 um for plated layers using the most advanced technology.
- Track thickness - again it goes down to 50/76 um with the best technology offered by Stevenage.
- Minimum mechanical hole - concerns TH vias. Goes down to 0.15 mm. It is very important to know that this is the size of the drill piece they use to drill the holes. If in Altium you have 0.2 mm via hole for example, that is the finished hole diameter after plating. Because of the plating thickness, they always need to use a bigger drill size, so there is enough space for the plating and after the plating you will get a finished hole diameter of 0.2 mm as desired. With one of my boards they needed to use 0.3 mm drills for the 0.2 mm via holes. We were fortunate that this was not a problem with the particular board, but it could be in many cases. So always keep that in mind when you set up rules and work out clearances.
- Minimum laser hole - concerns micro vias. Goes down to 60 um. The aspect ratio (depth to diameter) is quite small with micro vias (as Robert explains well in the Advanced Layout course) and that should be always considered. With Stevenage it can be up to 1.3:1. That means that if you have a micro via with a hole diameter of 0.1 mm it can go a maximum of 0.13 mm in depth. That will normally be just the distance between two layers next to each other. If you decide to go with a very small micro vias (0.06 mm lets say) you might found that they can't be long enough to connect two layers in your stack.
- Minimum micro via pad - goes down to 188 um for the surface layer (top/bottom) and 138 um for inner layers. Using vias in pads helps to gain additional space as well, to do some routing on the top layer, but requires a more advanced technology and might lead sometimes to problems with successful soldering of the BGA.
- Minimum solder mask expansion/Minimum solder mask sliver. If you use too small of a value for the expansion, you risk some pads to be partially covered by solder mask after manufacturing. If you use too small of a value for the solder mask sliver, you risk getting shorts between pads. To prevent such problems, I found it is a good practice for example to cover (tent) vias which are underneath a BGA. With Stevenage the minimum expansion you can have is 25 um and the minimum sliver is 76 um.
Again all of that should be checked with the particular manufacturer prior to starting the design, since as Robert explained you might easily find that they either can't manufacturer the board or the yield could be pretty low.