Routing DDR3 with another DDR3 chip for ECC using Flyby Top.
Dannyfey , 08-27-2019, 06:13 AM
I am working on a DSP board using TI's K2G processor. now, i was planning to use 4 DDR3L chips on both sides to save board space, like in the REX.
thing is, the K2G also supports a 4bit ECC, and they want me to keep that feature.
in the K2G Eval board, they placed all 5 DDR chips (4 + ECC) on one side of the board. i would prefer to avoid doing that.
while the Datasheet of the K2G talks about routing the memory in the double sided configuration, it doesnt say much about the ECC chip.
since the ECC chip breaks the nice symmetry i had in mind, i would like to double check before i go with my intuition.
I attached a drawing of what my intuition tells me i should do- adding the ECC chip next to the 4 other chips, length(delay) matching the address & control signals going from DDR IV to the ECC and placing all the terminations needed for Flyby Top. underneath the ECC chips.
what do you think?
Paul van Avesaath , 08-28-2019, 05:50 AM
i think that what you have drawn is the only way to do if you want to save board space..
robertferanec , 08-28-2019, 06:37 AM
I have never designed board with this configuration and I do not know the speed what you are going to use for the memories, but I am not sure about influence of stubs. For this configuration you will need to route into middle under the memory and then connect TOP and BOTTOM pins which are mirrored. In standard one side layout you can create very small stubs, in this configuration the stubs may be much longer and that may influence quality of the signal.
PS: You can use memory chips with two banks (but I guess that is what you are doing, just it is not in the picture).
Paul van Avesaath , 08-28-2019, 06:43 AM
I have done a similar design a while back but that whent only up to 1066 MHz on the data.. so 533Mhz clock.. there it worked fine.. but don't know about higher speeds because the FPGA did not support higher.. I believe it hsuld be fine upto 800Mhz.. but can not verify this.
robertferanec , 08-28-2019, 06:46 AM
I think 533MHz clock is generally ok ... but I am not sure about going above 900MHz clock
Dannyfey , 08-28-2019, 07:06 AM
the K2G processor I'm using supports 32bit data bus (split 8 bits for 4 chips) at speeds up to 533Mhz.
the data sheet talks about this mirrored configuration. my issue come from adding another ECC memory chip. the ECC memory has a 4bit data bus, but uses the same control and address lines as the other DDRs.
so if you'd look at the pictures i attached from the data sheet, what would happen if i add that ECC chip after the second duel chips (with A4 style length) and then the vias will connect to the termination. like i drew in the last pic?
robertferanec , 08-28-2019, 07:33 AM
But I am not sure if memory mirroring is working on 1 chipselect / rank (I guess that is what you are trying to do) .. meaning, I am not sure if you can apply mirroring only on specific chips. I think mirroring only works if you are using two different chipselects / ranks (so memory controller "mirrors" the specific address signals). Some time ago I created this post, it says "Mirroring is done on 2 rank modules and can only be done on the second rank": https://www.fedevel.com/welldoneblog...ng-pcb-layout/
Maybe consider going for 16bit chips, that will help you a lot.
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