Connecting Power net from bottom to top layer through via
SpikeHawk , 04-03-2021, 02:35 PM
I would like to connect a power signal (+5V) from bottom layer to top layer through via. In my first implementation (picture1) I am using a single via on the power track although I was thinking that I could place a polygon poor and use multiple vias in order to connect the power signal from the bottom into the top layer, in that way I could create a lower impedance path for the power signal so I could ensure a greater amperage capacity for the track. I don't think that this is necessary for the specific application since there is no need for high amperage capacity (<1.5A) but I would like to ask if that's a good practice in that type of connections?
robertferanec , 04-06-2021, 08:53 AM
I am not sure what exactly is then connected from the bottom track (e.g. if only 1 component or half of the board .... or if it is a standard board or a high speed design, etc). But, for a simple connection on a simple board, one VIA can be just fine. For more components, I would use polygons with multiple VIAs.
qdrives , 04-14-2021, 08:20 AM
On the prototypes build of my very first design there were "voids in the via's". Ever since I am very aware of via problems.
For power lines I generally use two via's to connect traces IF it continues on a different layer to multiple connections.
I also use(d) a simple rule of maximum 1A per via, so with 1.5A that already requires 2 via's. The best way to know how much current can go through a via is with the PCB toolkit (https://saturnpcb.com/saturn-pcb-toolkit/
) Now I am working on a design where the via's are smaller and even micro via's and there I limit it to 0.5A per via.
However, I do not use a polygon pour as a distribution point, but like the picture below.
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