Platform forum

VIA Location

JohnsonMiller , 02-23-2017, 06:06 AM
Hi Guys,

In multi-layer boards sometime we need to cut plane layer or use different polygons, it may happen that a via sits in separation area and cause manufacturing issue, following is an example which happened for me recently.

the VCC3V3 net is bottom side of figure so there was connection between via and plane, and it was reason that Altium did not report any violation, however after manufacturing we see e-test failure and has to re-manufacture the board.

My question is "do we have some design rule or any other means to find out vias which is placed in void area? or find out vias which do not have proper connection?"

mairomaster , 02-23-2017, 06:25 AM
I can't think of a rule to help you with that. Such issues are not hard to notice during the inspection of the layout, if done properly. With every single power polygon I would highlight the net and carefully inspect all connections on all layers (using single layer mode). I've never had similar issues.

Apart from that, many times you are using multiple vias per power net. Apart from increasing the ampacity, this will help in such situations as well.
JohnsonMiller , 02-23-2017, 11:46 AM
Thank you for your reply,
Manual inspection in multilayer board is not easy option.

The reported case was a 0603 ferrite bead fanout via and there was no need/space for multiple vias,

My main concern is a way to report partial connection,

Can I expect manufacturing test and related tools to do this level of inspection? tools that people use for Gerber mask check?

robertferanec , 02-23-2017, 04:14 PM
This is interesting. I do not know if there is a rule, but we are careful about this and we always double check layout to be sure all the VIAs are fully inside polygons and planes.
Also, I would expect manufacturer to notice this.
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