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## PCB Layout – Typical Track & VIA geometry

I have received following questions on our FEDEVEL forum:
What are typical track width you use for signal and for power ?
What are typical clearance you use for track ?
What are typical via size you use for normal via and for micro via ?

It’s not so simple to answer, so I decided to make a post about it. Here we go ….

## You may want to use two kind of PCBs

Track / Clearance
– Normally I start routing the digital signals with: 0.1mm / 0.1mm (4mil / 4mil) track width / clearance. When the layout is completely finished I decrease the track width to achieve 50OHM impedance (your PCB stackup has to be designed the way, that 50OHM tracks have 0.1mm width or less). This means, by the end of design I select all 0.1mm tracks (all the signals which should be routed by 50 OHM impedance) and I will make the tracks thinner e.g. I change the track with to 0.075mm / 3mil. This way, also clearance will increase a little bit.

Power Tracks
– Initially I set a rule for all power tracks to be at least 0.11mm (in our designs we set a rule for all the signals starting with “+” and for the “GND”). This is to be sure, there are no power tracks with 0.1mm (4mil) width (if there were, these tracks would be made thinner by the end of the design, see the previous point, and we do not really want to do that). To create high current connections, calculate the minimum track width (e.g. use Saturn PCB toolkit) to determine the minimum required track width for the maximum current flowing through the track. For standard power connections (e.g. decoupling capacitors) I usually use 0.2 or 0.3mm track width or I use the same track width as the pad is.

Power Polygons
– Don’t forget, even for polygons you need to calculate the maximum allowed current in the thinnest place of the polygon. For clearance between polygons we often use a bigger gap e.g. 0.2mm (8mil)

Power VIAs
In some designs we use bigger VIAs for powers, but most of the time we use multiple standard VIAs (see below)

Standard VIAs
– VIA and Buried VIA size / drill: 0.45mm / 0.2mm (18mil / 8mil)
– uVIA size / drill: 0.27mm / 0.1mm (11mil / 4mil)

Important! The parameters above depends on your PCB stackup. For example, to be able to use 0.1 drill for uVIAs, you may need to keep dielectricum thickness up to 0.1mm. If you like, you may want to have a loook at some of our stackups here: Download PCB Stackups – Free for your Projects

## PCB2 – The cost effective one

Track
– Track width and Clearance depends on PCB manufacturer. Usually, these cheap PCB manufacturers have limits for minimum track around 0.15mm (6mil), but you may want to route your board by 0.2mm (8mils). Once you decide on track width, you need to design your stackup the way, that your selected track width will be 50OHM (so you need to choose material with proper dielectricum Er and dielectricum thickness).

Clearance
– You may want to keep your minimum clearance at least as wide is the minimum track width. If it’s not possible and you need to use smaller clearance, go down to 0.1mm (4mils), but only in the critical places. Don’t forget to double check with your PCB manufacturer if they will be able to manufacture it.

Power Polygons
– The same as for PCB Type 1, don’t forget to calculate the maximum allowed current in the thinnest place of the polygon and you may want to use a bigger gap between polygons (e.g. set the minimum clearance between polygons to 0.2mm (8mils))

Power VIAs
In some designs we use bigger VIAs for powers, but most of the time we use multiple standard VIAs (see below)

Standard VIAs
– VIA size / drill: 0.45mm / 0.2mm (18mil / 8mil)

If you are still not sure, have a look at our open source projects. You can download complete Altium files of iMX6 Rex module (a design with uVIAs and Buried VIAs) or OpenRex (a design with through hole VIAs only). Then, just open the files and measure everything you need 🙂